| Online ISSN | : | 2953-7975 |
| Print ISSN | : | 1829-1740 |
Vol. 60 No. 2 (270) (2026): In process
Mathematics
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Mathematics
ON EDGE-CHROMATIC SUMS OF CORONA PRODUCTS OF GRAPHS
AbstractA proper edge-coloring of a graph $G$ is a mapping from its edges to the set of positive integers, so that adjacent edges receive different numbers (colors). If a proper edge-coloring of a graph $G$ minimizes the sum of colors on all edges, it is called a sum edge-coloring and the sum is called the edge-chromatic sum of $G$. In this paper, we study the connection between the edge-chromatic sum of corona product of graphs with the edge-chromatic sums of its factors. We provide general upper bounds on the edge-chromatic sum of corona products of graphs, as well as we prove that the edge-chromatic sum of the corona products of bipartite graphs and regular graphs of odd order can be exactly determined by the edge-chromatic sums of the factors.
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Informatics
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Informatics
PARALLEL 3D RECTILINEAR STEINER TREE CONSTRUCTION BASED ON SPANNING GRAPHS
AbstractSteiner tree construction is a fundamental problem in VLSI physical design. Given a set of pins in 3D space, the objective is to connect all pins with minimum total wirelength, possibly using additional Steiner points. This problem becomes particularly important in modern 3D integrated circuits, where vertical connections are realized through Through-Silicon Vias (TSVs). Since TSVs occupy valuable silicon area, their positions must be carefully determined and tracked to avoid conflicts between different nets. Building upon the 3D rectilinear spanning graph presented in prior work, this paper proposes a parallel algorithm for 3D rectilinear Steiner tree construction. The main contributions are as follows. First, the pair-generation process is decoupled from Kruskal's algorithm. Second, Tarjan's sequential lowest-common-ancestor (LCA) computation is replaced with the Euler tour technique combined with a range-minimum-query (RMQ) data structure, enabling fast and independent parallel LCA queries. In addition, a centroid-based tree partitioning scheme is introduced, which allows edge substitutions to be computed concurrently and independently. The proposed algorithm achieves up to $15\times$ speedup with 16 threads compared to the sequential version while maintaining solution quality. As an application, a TSV-aware multi-net routing framework is demonstrated, where dies are modeled as layers in 3D space, and TSV positions are dynamically determined during Steiner tree construction and tracked to prevent conflicts between nets.
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Lin C.-W., Huang S.-L., et al. Multilayer Obstacle-Avoiding Rectilinear Steiner Tree Construction Based on Spanning Graphs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27 (2008), 2007-2016. https://doi.org/10.1109/TCAD.2008.2006095
Wang R.-Y., et al. Efficient Multi-Layer Obstacle-Avoiding Region-to-Region Rectilinear Steiner Tree Construction. Proceedings of the 55th ACM/ESDA/IEEE Design Automation Conference (DAC). USA, CA, San Francisco (2018), 1-6.
Lee M.C., Jan G.E., Luo C.C. An Efficient Rectilinear and Octilinear Steiner Minimal Tree Algorithm for Multidimensional Environments. IEEE Access 8 (2020), 48141-48150. https://doi.org/10.1109/ACCESS.2020.2977825
Lin S.-E.D., Kim D.H. Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing. Proceedings of the International Symposium on Physical Design (ISPD) (2019), 57-64. https://doi.org/10.1145/3299902.3309749
Yan J.-T., Chen Z.-W., Hu D.-H. Timing-driven Steiner Tree Construction for Three-dimensional ICs. Proceedings of the IEEE International Conference on IC Design Technology (2008), 335-338. https://doi.org/10.1109/NEWCAS.2008.4606389
Tang H., Liu G., et al. A Survey on Steiner Tree Construction and Global Routing for VLSI Design. IEEE Access 8 (2020), 68593-68622. https://doi.org/10.1109/ACCESS.2020.2986138
Khachatryan R.N., Harutyunyan A.G. Parallelization of Rectilinear Minimum Spanning Tree Construction Algorithm. Proceedings of ISPC ``Modern Information and Electronic Technologies". Ukraine, Odesa (2025), 35-36. https://arar.sci.am/Content/427647/121-128.pdf
Harutyunyan A.G., Khachatryan R.N. ``Coarse-Grained Parallelization of the Spanning Graph Construction Algorithm. Proc. of the RA NAS and NPUA, Ser. of Technical Sciences 78 (2025), 121-128. https://doi.org/10.53297/0002306X-2025.v78.1-121
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